FIG. 1 (Prior Art) is a simplified diagram of a consumer market digital still camera 1. An image passes through lens 2 and is captured by an image sensor 3. Image sensor 3 may, for example, be a charge coupled device (CCD) sensor or a CMOS sensor or another type of sensor. In the present example, the sensor is a CCD sensor. An analog front end (AFE) and timing generator (TG) integrated circuit 4 supplies vertical pulse signals (VPULSE signals) and horizontal pulse signals (HPULSE signals) to sensor 3 such that the sensor data (CCD OUT) is read out of the sensor and is transferred to the AFE/TG 4. CCD sensor 3 requires vertical pulse signals whose voltage minimums and voltage maximums are outside the voltage range that can be supplied by the AFE/TG integrated circuit. The vertical pulse signals VPULSE output from the AFE/TG integrated circuit are therefore supplied to a vertical driver 5 that performs level shifting to the voltage levels required by the CCD sensor 3.
AFE/TG integrated circuit 4 digitizes the image data received from the sensor and passes the digitized image data to a digital image processing (DIP) integrated circuit 6. The digitized image data is denoted DOUT. DIP 6 performs image processing on the image data and then typically stores the image in digital form in mass storage 7. The information may, for example, be stored as a digital file. DIP 6 also causes the image to be displayed on a display 8. A microcontroller 9 provides overall key scanning, control and configuration functions for the camera. Microcontroller 9 is coupled to DIP 6 via a serial bus. Microcontroller 9 controls lens 2 via motor driver circuitry 10.
FIG. 2 (Prior Art) is a simplified diagram of a primitive CCD image sensor 11. CCD image sensor 11 includes a two-dimensional array of sensors. In the illustration, the sensors are denoted as squares, where each square contains a letter. A square that contains a “G” is a sensor for green. A square that contains an “R” is a sensor for red. A square that contains a “B” is a sensor for blue. Reference numeral 12 identifies one such sensor for green. In response to a shutter signal, each of the sensors takes a sample. The sample is retained in the sensor in the form of a charge. The magnitude of the charge indicates the sample value. The charge values are read out of CCD sensor 11 in serial fashion by supplying horizontal pulse signals and vertical pulse signals to the CCD sensor. Each sensor has an associated storage element located to its left. Reference numeral 13 identifies the storage element for sensor 12. At one time, the sample charges from all the sensors are transferred right to left into the associated storage elements. A vertical pulse signal is then applied to CCD sensor 11. This causes the sample charge in each storage element to be shifted down to the storage element below it. The sample charge in the bottom-most row of storage elements passes into a row 14 of storage elements at the bottom of the sensor. Once this row 14 contains a set of charges, a plurality of horizontal pulses is applied to CCD sensor 11. These horizontal pulses cause the sample charges in the storage elements of row 14 to be shifted out of the CCD sensor one-by-one. When the complete row of sample charges has been shifted out of CCD sensor 11, then another vertical pulse is applied to load row 14 with the next row of sample charges to be read out. This process of supplying a vertical pulse, and then shifting out the bottom row of sample charges is repeated until all the sample charges are read out of CCD sensor 11.
FIG. 3 (Prior Art) is a simplified diagram that illustrates an operation of row 14 of storage elements. To transfer a charge from storage element 15 to storage element 16, switch 17 is opened and switch 18 is closed. This allows charge from storage element 15 to pass through conductive switch 18 and into storage element 16. It is therefore seen that adjacent switches in the row are opened and closed in alternating fashion to shift a sample charge down the row of storage elements. It is to be understood that FIG. 3 is a very simplified diagram presented here for background information.
FIG. 4 (Prior Art) illustrates the alternating fashion of pulses in the two horizontal pulse signals HPULSE1A and HPULSE1B that control the row of switches of FIG. 3.
FIG. 5 (Prior Art) is a simplified diagram of a slightly more complex CCD sensor 19. In CCD sensor 19, each successive pair of columns of sensors shares a column of storage elements. Columns V1A and V1B share one column of storage elements. Columns V2A and V2B share a second column of storage elements.
FIG. 6 (Prior Art) illustrates the vertical pulse signals VPULSE1A and VPULSE1B used to read the sensor samples out of the array. First, the left column of sensors of each successive pair of columns is to be read out. The right column of sensors of each pair is not read out. The initial high pulse 20 of VPULSE1A with no such high pulse of VPULSE1B indicates that the left column of sensors is to transfer a column of sample charges to the center column of storage elements. Once this transfer occurs, the VPULSE1A and VPULSE1B alternate as in FIG. 4 to shift the sample charges down in the vertical dimension. After each such vertical shift, a complete set 21 of horizontal shift pulses of HPUSEL1A and HPULSE1B shifts out the bottom row of storage elements of the sensor.
Once this left half of the image frame has been shifted out, then a high pulse 22 on VPULUSE1B causes the right column of sensors of each pair of sensor columns to transfer their sample charges to the shared column of storage elements. The process repeats with each vertical shift being followed by a set 21 of horizontal shift pulses. In this way, sample charges from sensors in the right column of each pair of sensor columns is read out of CCD sensor 19. It is therefore seen that more complex vertical and horizontal shift pulses are required for a CCD sensor having such shared columns of storage elements.
The state of the art in CCD image sensors has advanced well beyond the simple examples set forth in FIGS. 2-6. Sensors typically have multiple modes including, for example, a high frame rate readout mode, an autoexposure and autofocus mode, and a capture mode. As a result, quite complex timing signals are often required to drive contemporary CCD sensors. The high frame rate readout mode may, for example, be used in a hybrid camera when the hybrid camera is used to capture video, whereas the higher resolution capture mode may be used when the hybrid camera is used to take still pictures.
FIG. 7 (Prior Art) illustrates a CCD sensor 23 that requires somewhat more complex timing signals. CCD sensor 23 has a high-speed readout mode wherein pixel mixing is performed. To increase the readout rate of a pixel image, only some of the image sensor samples captured may be read out of the sensor. This reduces the amount of information to be output from the sensor and therefore decreases readout time, but it may cause an undesirable amount of image degradation. If only a subset of the sample charges are output, then image information captured in the other unused local sensors will not be present in the image data as the image data is output from the sensor. Rather than failing to include this image information in the high readout speed mode image, an improved high-speed readout mode image may be had by mixing samples for the local set of sensors, and then shifting out the mixed result. Arrows 24 and 25 illustrate a mixing of two green sensor samples in the top row of sensors. Similarly, arrows 26 and 27 illustrate a mixing of two blue sensor samples in the second row of sensors. At a later stage, vertical mixing may take place as illustrated by arrows 28 and 29. Rather than simply outputting one sample charge from one sensor of a group of sensors and ignoring the sample charges output by other sensors of the group, the sample charges of all the sensors of the group are mixed (using both horizontal and vertical mixing) to improve the quality of the high frame rate readout image.
FIG. 8 (Prior Art) illustrates the more complex timing pulses required to perform this readout. High pulses 30 and 31 on both vertical pulse signals VPULSE1A and VPULSE1B at the same time indicates the horizontal sample mixing operation. The horizontally mixed sample charges, once in the center column of storage elements, are shifted down as set forth above in connection with FIG. 5 by the alternating pulse trains on VPULSE1A and VPULSE1B. Following each vertical shift, a sequence of horizontal shifts of HPULSE1A and HOPULSE1B shifts a mixed row of sample charges out of the CCD sensor.
Due to the complexity of the timing signals required by a typical contemporary CCD sensor, a CCD sensor manufacturer typically also supplies a compatible timing generator integrated circuit for use with the CCD sensor. Accordingly, each CCD sensor typically has its own specific timing generator. This solution to supplying a circuit for generating the needed timing signals can work well in situations where a camera design is only to include one possible type of CCD sensor. For situations in which a choice of any one of multiple different CCD sensors is to be used, however, an AFE/TG integrated circuit having a programmable timing generator is available.
FIG. 9 (Prior Art) is a simplified diagram that illustrates how complex timing signals can be defined in such an AFE/TG. First, a set of signal patterns is defined. In the illustration, VPAT0 is a first pattern, and VPAT1 is a second pattern. Each pattern defines transitions for signals. In the example illustrated, the signals are vertical pulse signals V1-V4. Sequences are then built from the patterns. In the illustration, V-SEQUENCE0 involves repeating VPAT0 N times. V-SEQUENCE1 involves starting with VPAT0 and then ending with VPAT1. The sequences are then associated with different readout regions and fields. A field may contain multiple regions. A different sequence can, for example, be associated with each region where each sequence defines a unique pulse pattern. A typical still digital camera may, for example, require a first field timing for a draft mode, a second field timing for an autofocus mode, and three different field timings for an ordinary image capture mode. During camera operation, a value loaded into a mode register selects which field timing is active, depending on how the camera is being used. For one particular example of a AFE/TG integrated circuit made for use with different CCD sensors, see the “AD9995 12-Bit CCD Signal Processor With Precision Timing Generator” data sheet, Analog Devices Inc., 36 pages, Rev. 0, copyright 2003 (the subject matter of which is incorporated herein by reference).
FIG. 10 (Prior Art) illustrates how three such AFE/TGs 32-34 can be used in a digital still camera. Each AFE/TG receives CCD data from its own CCD image sensor. There is an image sensor for red, one for green and one for blue. AFE/TG 32 supplies a 16-bit red pixel output value to DIP 35 via 16-bit bus 36, multiplexing circuitry 37, and 16-bit bus 38. Next, AFE/TG 33 supplies a 16-bit green pixel output value to DIP 35 via 16-bit bus 39, multiplexing circuitry 37, and 16-bit bus 38. Next, AFE/TG 34 supplies a 16-bit blue pixel output value to DIP 35 via 16-bit bus 40, multiplexing circuitry 37, and 16-bit bus 38. This order of outputting pixel values in the order red, green, blue, red, green, blue etc. continues pixel value by pixel value until all the pixel values of the frame have been transferred to DIP 35.
The architecture of this type of AFE/TG is flexible and works in several applications with several difference CCD sensors. Its programming and operation is, however, somewhat idiosyncratic making it difficult to use. Moreover, there are timing signal requirements and other functionalities and operating modes that the AFE/TG design does not support. For example, stability control may require changing the number of pulses in certain timing signals from one frame to the next when video is being captured. Only a portion of the CCD sensor may be used when taking video. This portion may shift around within the CCD sensor as the user inadvertently moves the camera when taking video. This shifting from frame to frame may introduce undesired jitter into the video. So that the jitter is not seen, it may be desired to change the timing signals supplied to the sensor so that the area of the sensor being used does not appear to shift from one frame to the next. The AFE/TG does not, however, have an ability to receive stability control information on a frame-by-frame basis such that the AFE/TG can generate stability-corrected timing signals that are modified on a frame-by-frame basis. If such a stability control feature were to be supported, then the AFE/TG design would have to be modified. This stability feature is but one feature not supported by the AFE/TG design. Accordingly, as CCD sensors advance in complexity and as CCD sensor timing signal requirements proliferate, the AFE/TG will probably have to be changed over and over through the years in order for the AFE/TG to be able to generate all the timing signals needed to drive the new CCD sensors.